In a power semiconductor device constituted by a power vertical metal oxide semiconductor field effect transistor (MOSFET) described in Patent Document 1 and a diode, the diode is disposed in at least one line in an adjacent region to a peripheral edge part of a cell region of the MOSFET, that is, a gate pad portion as shown in FIGS. 1 and 2 of the same Document. Each diode absorbs a hole injected in a forward bias from a P well and a P base into an N-type semiconductor layer on a drain side as shown in FIG. 2 of the same Document when the MOSFET is switched from an ON state to an OFF state. For this reason, the structure disclosed in the same Document can prevent a parasitic transistor shown in FIG. 3 of the same Document from being turned ON when the MOSFET is switched from the forward bias to a reverse bias.
With the structure in the same Document, the P base to be the P well of the MOSFET is electrically connected to a source electrode through a back gate as shown in FIG. 2.